Russian Federation
Russian Federation
Russian Federation
004.021
Purpose: To develop a method for increasing the speed of CRC computation for programmable logic integrated circuits (PLICs) that exceeds the speed of the direct computation method by cyclic shift. Methods: Computer simulation has been used for experimental studies. The analytical review method and the theory of noise protection coding have been used for theoretical studies. Results: A CRC calculation method for constant length messages using arbitrary polynomials is proposed and described. Control digit codes with minimum redundancy and cyclic redundant codes have been compared and the results are presented. Practical significance: The method described allows for a qualitatively faster CRC calculation based on FPGAs than those previously used. A method for accelerating the calculation of cyclic redundancy code for arbitrary polynomials has been developed provided that the message length is fixed.
Anti-jamming coding, cyclic redundancy code, FPGA, code distance, separable codes
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