Self-Checking Discrete Device Synthesis Using Parity Code Properties and Self-Duality Boolean Functions

Dmitriy Efanov

doi:10.20295/2412-9186-2025-11-03-264-279

UDC 004.052.32 UDC 681.518.5

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SELF-CHECKING DISCRETE DEVICE SYNTHESIS USING PARITY CODE PROPERTIES AND SELF-DUALITY BOOLEAN FUNCTIONS Self-Checking Discrete Device Synthesis Using Parity Code Properties and Self-Duality Boolean Functions

АА Аа

Published in Transport automation research · Volume 11, Issue 3 · Pages 264–279 · Rubric: TECHNICAL DIAGNOSTICS AND CONTROLLABLE SYSTEMS

DOI: https://doi.org/10.20295/2412-9186-2025-11-03-264-279

Received: 17.09.2025 Accepted: 17.09.2025 Published: 17.09.2025

Authors

Dmitriy Efanov

Academic degree: doctor of technical sciences

Science rang: professor

Peter the Great Saint Petersburg Polytechnic University Professor · Higher School of Cyberphysical Systems & Control, Institute of Computer Science and Cybersecurity · Russian Federation

Peter the Great Saint Petersburg Polytechnic University Professor · Higher School of Transport, Mechanical Engineering, Material and Transport Institute · Russian Federation · Saint-Petersburg

Russian University of Transport (MIIT) Professor · Department of Automation, Remote Control and Communication on Railway Transport · Russian Federation · Moscow

Tashkent State Transport University Professor · Department of Automation and Remote Control · Uzbekistan · Tashkent

Institute of Transport Problems named after N. S. Solomenko of the Russian Academy of Sciences Leading Researcher · Laboratory of Problems of Organization of Transport Systems (Laboratory No. 5) · Russian Federation

ABSTRACT

Abstract: The paper demonstrates that the established organizational structure of the concurrent error-detection circuit, founded on the self-duality feature with preliminary signal compression from the diagnostic object employing the parity function (a modified parity control structure), enables the comprehensive self-checking discrete devices for specific initial objects. As demonstrated, when conducting control checking calculations based on the self-duality feature with preliminary compression of signals from the diagnostic object by parity, faults in the modulo-2 addition gates of the parity code encoder are not detected. This is provided that the parity of the sub-vector of the data vector, generated at outputs connected by paths with the failed gate, remains unchanged. This imposes certain restrictions on the use of the established modified parity control structure in the self-checking discrete device synthesis. The paper presents a further modification to the parity testing structure. The proposed structure overcomes the known structure’s drawback by ensuring calculation control through both parity and assigning the function describing the control output to the class of self-dual Boolean functions. Due to the minor complication of the CED circuit compared to the parity check circuit, it is possible to significantly improve the testability characteristics. Further studies of the new organization structure of CED parity check circuits will allow us to determine the criteria of its applicability in the self-checking discrete device synthesis.

KEYWORDS

discrete device fault detection; self-checking discrete device; Boolean complement self-duality control; parity computing check; concurrent error-detection circuit; control circuit component testability

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GOST

Efanov D. V. Self-Checking Discrete Device Synthesis Using Parity Code Properties and Self-Duality Boolean Functions // Transport automation research. 2025. no. 3. pp. 264-279. DOI: https://doi.org/10.20295/2412-9186-2025-11-03-264-279. (Date of access 19.10.2026).

MLA

Dmitriy Efanov. "Self-Checking Discrete Device Synthesis Using Parity Code Properties and Self-Duality Boolean Functions." Transport automation research 11.3 (2025): 264-279. DOI: https://doi.org/10.20295/2412-9186-2025-11-03-264-279.

APA

Efanov D. V. (2025). Self-Checking Discrete Device Synthesis Using Parity Code Properties and Self-Duality Boolean Functions. Transport automation research, 11(3), 264-279. https://doi.org/10.20295/2412-9186-2025-11-03-264-279

Chicago

Dmitriy Efanov. "Self-Checking Discrete Device Synthesis Using Parity Code Properties and Self-Duality Boolean Functions." Transport automation research 11, no. 3 (2025): 264-279. https://doi.org/10.20295/2412-9186-2025-11-03-264-279.

WIKI

{{cite journal | author = Efanov D. V. | title = Self-Checking Discrete Device Synthesis Using Parity Code Properties and Self-Duality Boolean Functions | journal = Transport automation research | year = 2025 | volume = 11 | issue = 3 | pages = 264-279 | doi = 10.20295/2412-9186-2025-11-03-264-279 }}

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SELF-CHECKING DISCRETE DEVICE SYNTHESIS USING PARITY CODE PROPERTIES AND SELF-DUALITY BOOLEAN FUNCTIONS Self-Checking Discrete Device Synthesis Using Parity Code Properties and Self-Duality Boolean Functions

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